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NTB30N20 Power MOSFET 30 Amps, 200 Volts
N-Channel Enhancement-Mode D2PAK
Features
* Source-to-Drain Diode Recovery Time Comparable to a Discrete * * *
Fast Recovery Diode Avalanche Energy Specified IDSS and RDS(on) Specified at Elevated Temperature Mounting Information Provided for the D2PAK Package
VDSS 200 V
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RDS(ON) TYP 68 m @ VGS = 10 V
ID MAX 30 A
Typical Applications
* PWM Motor Controls * Power Supplies * Converters
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Rating Drain-to-Source Voltage Drain-to-Source Voltage (RGS = 1.0 M) Gate-to-Source Voltage - Continuous - Non-Repetitive (tpv10 ms) Drain Current - Continuous @ TA 25C - Continuous @ TA 100C - Pulsed (Note 2) Total Power Dissipation @ TA = 25C Derate above 25C Total Power Dissipation @ TA = 25C (Note 1) Operating and Storage Temperature Range Single Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 100 Vdc, VGS = 10 Vdc, IL(pk) = 20 A, L = 3.0 mH, RG = 25 ) Thermal Resistance - Junction-to-Case - Junction-to-Ambient - Junction-to-Ambient (Note 1) Maximum Lead Temperature for Soldering Purposes for 10 seconds Symbol VDSS VDGR VGS VGSM ID ID IDM PD PD TJ, Tstg EAS 450 C/W RJC RJA RJA TL 0.7 62.5 50 260 C Value 200 200 "30 "40 Adc 30 22 90 214 1.43 2.0 -55 to +175 W W/C W C mJ 1 2 3 D2PAK CASE 418B STYLE 2 Unit Vdc Vdc Vdc G
N-Channel D
S
MARKING DIAGRAM & PIN ASSIGNMENT
4 Drain 4 NTB30N20 LLYWW
1 Gate
2 Drain
3 Source
NTB30N20 LL Y WW
= Device Code = Location Code = Year = Work Week
ORDERING INFORMATION
Device NTB30N20 NTB30N20T4 Package D2PAK D2PAK Shipping 50 Units/Rail 800 Tape & Reel
1. When surface mounted to an FR4 board using the minimum recommended pad size, (Cu Area 0.412 in2). 2. Pulse Test: Pulse Width = 10 s, Duty Cycle = 2%.
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D.
(c) Semiconductor Components Industries, LLC, 2004
1
April, 2004 - Rev. 3
Publication Order Number: NTB30N20/D
NTB30N20
ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) Zero Gate Voltage Collector Current (VGS = 0 Vdc, VDS = 200 Vdc, TJ = 25C) (VGS = 0 Vdc, VDS = 200 Vdc, TJ = 175C) Gate-Body Leakage Current (VGS = 30 Vdc, VDS = 0) ON CHARACTERISTICS Gate Threshold Voltage VDS = VGS, ID = 250 Adc) Temperature Coefficient (Negative) Static Drain-to-Source On-State Resistance (VGS = 10 Vdc, ID = 15 Adc) (VGS = 10 Vdc, ID = 10 Adc) (VGS = 10 Vdc, ID = 15 Adc, TJ = 175C) Drain-to-Source On-Voltage (VGS = 10 Vdc, ID = 30 Adc) Forward Transconductance (VDS = 15 Vdc, ID = 15 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance (VDS = 25 Vdc, VGS = 0 Vdc, f = 1.0 MHz) (VDS = 25 Vdc, VGS = 0 Vdc, f = 1.0 MHz) (VDS = 160 Vdc, VGS = 0 Vdc, f = 1.0 MHz) (VDS = 25 Vdc, VGS = 0 Vdc, f = 1.0 MHz) Ciss Coss Crss - - - - 2335 380 148 75 - - - - pF VGS(th) 2.0 - RDS(on) - - - VDS(on) - gFS - 2.0 20 2.5 - Mhos 0.068 0.067 0.200 0.081 0.080 0.240 Vdc 2.9 -8.9 4.0 - Vdc mV/C V(BR)DSS 200 - IDSS - - IGSS - - - - 5.0 125 100 nAdc - 307 - - Vdc mV/C Adc Symbol Min Typ Max Unit
SWITCHING CHARACTERISTICS (Notes 3 & 4) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Gate Charge (VDS = 160 Vdc, ID = 30 Adc, VGS = 10 Vdc) (VDS = 160 Vdc, ID = 18 Adc, VGS = 5.0 Vdc) 50 BODY-DRAIN DIODE RATINGS (Note 3) Forward On-Voltage Reverse Recovery Time (IS = 30 Adc, VGS = 0 Vdc, Ad Vd dIS/dt = 100 A/s) Reverse Recovery Stored Charge 3. Indicates Pulse Test: P. W. = 300 s max, Duty Cycle = 2%. 4. Switching characteristics are independent of operating junction temperature. (IS = 30 Adc, VGS = 0 Vdc) (IS = 30 Adc, VGS = 0 Vdc, TJ = 150C) VSD trr ta tb QRR - - - - - - 0.91 0.80 230 140 85 1.85 1.1 - - - - - C Vdc ns td(on) (VDD = 100 Vdc, ID = 18 Adc, , ) VGS = 5.0 Vdc, RG = 2.5 ) (VDD = 160 Vdc, ID = 30 Adc, VGS = 10 Vdc, RG = 9.1 ) tr td(off) tf Qtot Qgs Qgd - - - - - - - - - - - - - 10 12 20 70 40 82 24 88 75 48 20 16 32 - - - - - - - - 100 - - - - nC ns
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NTB30N20
60 ID, DRAIN CURRENT (AMPS) 50 40 7V 30 5V 20 10 4V 0 0 2 4 6 8 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 10 0 0 VGS = 10 V 9V TJ = 25C 8V 60 ID, DRAIN CURRENT (AMPS) 6V 50 40 30 20 TJ = 25C 10 TJ = 100C TJ = -55C 10 VDS 10 V
2 4 6 8 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)
Figure 1. On-Region Characteristics
RDS(on), DRAIN-TO-SOURCE RESISTANCE (W) RDS(on), DRAIN-TO-SOURCE RESISTANCE (W)
Figure 2. Transfer Characteristics
0.2 VGS = 10 V 0.15 TJ = 100C
0.1 TJ = 25C 0.09 VGS = 10 V VGS = 15 V 0.07
0.08
0.1
TJ = 25C
0.05
TJ = -55C
0.06 0.05
0
5
15
25 35 45 ID, DRAIN CURRENT (AMPS)
55
5
15
25 35 45 ID, DRAIN CURRENT (AMPS)
55
RDS(on), DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)
Figure 3. On-Resistance versus Drain Current and Temperature
Figure 4. On-Resistance versus Drain Current and Gate Voltage
3 2.5 2 1.5 1 0.5 0 -50 -25 ID = 15 A VGS = 10 V
100000
VGS = 0 V TJ = 175C
IDSS, LEAKAGE (nA)
10000
1000 TJ = 100C 100
0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (C)
175
10
20
40 60 80 100 120 140 160 180 200 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
Figure 5. On-Resistance Variation with Temperature
Figure 6. Drain-to-Source Leakage Current versus Voltage
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NTB30N20
POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge a voltage corresponding to the off-state condition when controlled. The lengths of various switching intervals (t) calculating td(on) and is read at a voltage corresponding to the are determined by how fast the FET input capacitance can on-state when calculating td(off). be charged by current from the generator. At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET The published capacitance data is difficult to use for source lead, inside the package and in the circuit wiring calculating rise and fall because drain-gate capacitance which is common to both the drain and gate current paths, varies greatly with applied voltage. Accordingly, gate produces a voltage at the source which reduces the gate drive charge data is used. In most cases, a satisfactory estimate of current. The voltage is determined by Ldi/dt, but since di/dt average input current (IG(AV)) can be made from a is a function of drain current, the mathematical solution is rudimentary analysis of the drive circuit so that complex. The MOSFET output capacitance also t = Q/IG(AV) complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the During the rise and fall time interval when switching a resistance of the driving source, but the internal resistance resistive load, VGS remains virtually constant at a level is difficult to measure and, consequently, is not specified. known as the plateau voltage, VSGP. Therefore, rise and fall The resistive switching time variation versus gate times may be approximated by the following: resistance (Figure 9) shows how typical switching tr = Q2 x RG/(VGG - VGSP) performance is affected by the parasitic circuit elements. If tf = Q2 x RG/VGSP the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. where The circuit used to obtain the data is constructed to minimize VGG = the gate drive voltage, which varies from zero to VGG common inductance in the drain and gate circuit loops and RG = the gate drive resistance is believed readily achievable with board mounted and Q2 and VGSP are read from the gate charge curve. components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which During the turn-on and turn-off delay times, gate current is approximates an optimally snubbed inductive load. Power not constant. The simplest calculation uses appropriate MOSFETs may be safely operated into an inductive load; values from the capacitance curves in a standard equation for however, snubbing reduces switching losses. voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP)
6000 5000 C, CAPACITANCE (pF) 4000 3000
VDS = 0 V Ciss
VGS = 0 V
TJ = 25C
Crss 2000 1000 Crss 0 0 5 VGS 0 VDS 5 10 15
Ciss
Coss 20 25
GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
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NTB30N20
VGS GATE-TO-SOURCE VOLTAGE (VOLTS) , 12 VDS QT 180 150 120 Q1 Q2 VGS 90 60 ID = 30 A TJ = 25C 30 0 70 1000 VDD = 160 V ID = 30 A VGS = 10 V 100 t, TIME (ns) tr td(off) 10 td(on) tf VDS,DRAIN-TO-SOURCE VOLTAGE (VOLTS)
10 8 6 4 2 0 0
10
20 30 40 50 QG, TOTAL GATE CHARGE (nC)
60
1
1
10 RG, GATE RESISTANCE ()
100
Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge
Figure 9. Resistive Switching Time Variation versus Gate Resistance
DRAIN-TO-SOURCE DIODE CHARACTERISTICS
30 IS, SOURCE CURRENT (AMPS) 25 20 15 10 5 0 0.5 VGS = 0 V TJ = 25C
0.6 0.7 0.8 0.9 VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)
1
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance-General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A Power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain-to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.
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NTB30N20
SAFE OPERATING AREA
E , SINGLE PULSE DRAIN-TO-SOURCE AS AVALANCHE ENERGY (mJ) 1000 I D, DRAIN CURRENT (AMPS) VGS = 20 V SINGLE PULSE TC = 25C 500 ID = 30 A 400
100
10 s 100 s
300 200
10 1 ms 10 ms 1 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT dc
100
0.1 0.1
1.0 10 100 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
1000
0 25
175 50 75 100 125 150 TJ, STARTING JUNCTION TEMPERATURE (C)
r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED)
Figure 11. Maximum Rated Forward Biased Safe Operating Area
Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature
1.0 D = 0.5
0.2 0.1 0.1 0.05 0.02 0.01 SINGLE PULSE 0.01 0.00001 0.0001 0.001 t1 t2 DUTY CYCLE, D = t1/t2 0.01 t, TIME (s) 0.1 P(pk) RJC(t) = r(t) RJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RJC(t)
1.0
10
Figure 13. Thermal Response
di/dt IS trr ta tb TIME tp IS 0.25 IS
Figure 14. Diode Reverse Recovery Waveform
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NTB30N20
PACKAGE DIMENSIONS
D2PAK CASE 418B-04 ISSUE H
C E -B-
4 DIM A B C D E F G H J K L M N P R S V NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. 418B-01 THRU 418B-03 OBSOLETE, NEW STANDARD 418B-04. INCHES MIN MAX 0.340 0.380 0.380 0.405 0.160 0.190 0.020 0.035 0.045 0.055 0.310 0.350 0.100 BSC 0.080 0.110 0.018 0.025 0.090 0.110 0.052 0.072 0.280 0.320 0.197 REF 0.079 REF 0.039 REF 0.575 0.625 0.045 0.055 GATE DRAIN SOURCE DRAIN MILLIMETERS MIN MAX 8.64 9.65 9.65 10.29 4.06 4.83 0.51 0.89 1.14 1.40 7.87 8.89 2.54 BSC 2.03 2.79 0.46 0.64 2.29 2.79 1.32 1.83 7.11 8.13 5.00 REF 2.00 REF 0.99 REF 14.60 15.88 1.14 1.40
V W
A
1 2 3
S
-T-
SEATING PLANE
K G D H
3 PL M
W J
0.13 (0.005) VARIABLE CONFIGURATION ZONE L M M
TB
M
R
N U L M
P L
STYLE 2: PIN 1. 2. 3. 4.
F VIEW W-W 1
F VIEW W-W 2
F VIEW W-W 3
SOLDERING FOOTPRINT*
0.33 8.38
0.42 10.66 0.04 1.016 0.12 3.05 0.67 17.02
0.24 6.096
inches mm
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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NTB30N20
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NTB30N20/D

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